Synopsis HAPS FPGA-Based Prototyping Solution 4-modules

It should be a HAPS 70 model.

HAPS‑70 Series Modules

• Capacity variations : Models span from 12M to 144M ASIC gates , using from 1 to 12 Xilinx Virtex‑7 2000T FPGAs—e.g., S12 (12 M), S24 (2 FPGA, 24 M), up to S144 (12 FPGA, 144 M)

• High‑speed I/O : All modules feature HapsTrak 3 connectors and HSTDM (High-Speed Time-Domain Multiplexing), with inter-FPGA bandwidth up to 1 Gbps , yielding up to 3× performance over older systems

• Rapid bring‑up : Synopsys’s ProtoCompiler automates partitioning and pin multiplexing. Multi-FPGA prototypes (even ~96 M gates across 8 FPGAs) can compile in under a day

• Deep‑trace debug : Off‑FPGA memory enables capture of thousands of signals or seconds of trace per FPGA—~100× greater visibility

• Hybrid support : Native UMRBus (up to 400 MB/s), SCE‑MI, and co‑simulation capabilities allow seamless integration with virtual prototypes and IP subsystems